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74AC20 Dual 4-Input NAND Gate
November 1988 Revised November 1999
74AC20 Dual 4-Input NAND Gate
General Description
The AC20 contains four 4-input NAND gates.
Features
s ICC reduced by 50% s Outputs source/sink 24 mA
Ordering Code:
Order Number 74AC20SC 74AC20SJ 74AC20MTC 74AC20PC Package Number M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names An, Bn, Cn, Dn On Description Inputs Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 1999 Fairchild Semiconductor Corporation
DS009918
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74AC20
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140C 50 mA -65C to +150C 50 mA -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V -0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V 2.0V to 6.0V 0V to VCC 0V to VCC -40C to +85C 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 4) IOLD IOHD ICC (Note 4) Maximum Input Leakage Current Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 2.0 0.002 0.001 0.001 TA = +25C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 VIN = VIL or VIH 0.44 0.44 0.44 1.0 75 -75 20.0 A mA mA A V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT = 50 A V IOH = -12 mA IOH = -24 mA IOH = -24 mA (Note 2) V IOUT = -50 A V VOUT = 0.1V or VCC - 0.1V V VOUT = 0.1V or VCC - 0.1V Units Conditions
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC20
AC Electrical Characteristics
VCC Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay (V) (Note 5) 3.3 5.0 3.3 5.0
Note 5: Voltage Range 3.3 is 3.3V 0.3V Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Min 2.0 1.5 1.5 1.5 Typ 6.0 5.0 5.0 4.0 Max 8.5 7.0 7.0 6.0
TA = -40C to +85C CL = 50 pF Min 1.5 1.0 1.0 1.0 Max 10.0 8.0 9.0 7.0 ns ns Units
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 40.0 Units pF pF VCC = OPEN VCC = 5.0V Conditions
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74AC20
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body Package Number M14A
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74AC20
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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74AC20
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
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74AC20 Dual 4-Input NAND Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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